/*???????????????????????????????????????????????????????????????????????????????*/
/* ac97codec.c V1.00 */
/* Copyright (c) 2001 Texas Instruments Incorporated */
/*???????????????????????????????????????????????????????????????????????????????*/
/*
6/12/01: Vassos S. Soteriou
ac97codec.c:
This program sets the McBSP of the TMS320C6000 devices as a digital
controller for an Audio Codec 1997 device. This program supports
all the Texas Instruments TMS320C6000 DSPs, those that use the DMA
controller or the Enhanced DMA controller (EDMA). For those that use
the DMA controller, DMA channels 1 and 2 service the McBSP.
CLKX, CLKR are generated using the CLKS clock.
FSX is the output that drives the codec’s frame syncs.
In the case of a DMA transfer, the vecs.asm assembly code file is
used to hookup the c_int11() and c_int09() ISRs to the corresponding
interrupts. Channel 1 is hooked up to interrupt 9 for data receive,
channel 2 is hooked up to interrupt 11 for data transmit, the DMA
controller has individual interrupts for each DMA channel. The EDMA
controller, however, generates a single interrupt to the CPU (EDMA_INT)
on behalf of all 16 channels (C621x/C671x) or 64 channels (C64x). The
various control registers and bit fields facilitate EDMA interrupt
generation. CPU_INT8 is responsible for all the EDMA channels
The sample code is based on TI’s CSL 2.0. Please refer to the TMS320C6000
Chip Support Library API User’s Guide for further information.
*/
/* Chip definition, change this accordingly */
#define CHIP_6415 1
/* Include files */
#include <c6x.h>
#include <csl.h> /* CSL library */
#include <csl_dma.h> /* DMA_SUPPORT */
#include <csl_edma.h> /* EDMA_SUPPORT */
#include <csl_irq.h> /* IRQ_SUPPORT */
#include <csl_mcbsp.h> /* MCBSP_SUPPORT */
#include <csl_timer.h> /* TIMER_SUPPORT */
/*???????????????????????????????????????????????????????????????????????????????*/
/* Define constants */
#define FALSE 0
#define TRUE 1
#define DMA_AC97 8
#define XFER_TYPE DMA_AC97
#define BUFFER_SIZE 256
#define ELEMENT_COUNT 13 /* Do not change this, AC’97 protocol */
#define FRAME_COUNT 10 /* Change this to desired value */
/* Global variables used in interrupt ISRs */
volatile int recv0_done = FALSE;
volatile int xmit0_done = FALSE;
/*???????????????????????????????????????????????????????????????????????????????*/
/* Declare CSL objects */
MCBSP_Handle hMcbsp0; /* Handles for McBSP */

//#if (EDMA_SUPPORT) /* Handles for EDMA */
EDMA_Handle hEdma1;
EDMA_Handle hEdma2;
EDMA_Handle hEdmadummy;
//#endif
TIMER_Handle hTimer0; /* Handle for TIMER0 */
/*???????????????????????????????????????????????????????????????????????????????*/
/* External functions and function prototypes */
void init_mcbsp0_ac97(void); /* Function prototypes */
//void set_interrupts_dma(void);
void set_interrupts_edma(void);
/* Inlcude the vector table to call the IRQ ISRs hookup */
extern far void vectors();
/*???????????????????????????????????????????????????????????????????????????????*/
/* main() */
/*???????????????????????????????????????????????????????????????????????????????*/
void main(void)
{
/* Declaration of local variables */
static int element_count, frame_count, xfer_type;
int delay_count = 0;
static Uint32 dmaInbuff[BUFFER_SIZE]; /* buffer for DMA supporting devices */
static Uint32 dmaOutbuff[BUFFER_SIZE];
static Uint32 edmaInbuff[BUFFER_SIZE]; /* buffer for EDMA supporting devices */
static Uint32 edmaOutbuff[BUFFER_SIZE];
IRQ_setVecs(vectors); /* point to the IRQ vector table */
element_count = ELEMENT_COUNT;
frame_count = FRAME_COUNT;
xfer_type = XFER_TYPE;
/* initialize the CSL library */
CSL_init();
/* Reset AC97 device */
/* Handle to TIMER 0, reset it upon open */
hTimer0 = TIMER_open(TIMER_DEV0, TIMER_OPEN_RESET);
TIMER_setDataOut(hTimer0,0); /* Write a 0 to the TOUT0 */
TIMER_start(hTimer0); /* Need to be 0 for at least 1 usec */
init_mcbsp0_ac97();
/* Enable sample rate generator GRST=1 */
MCBSP_enableSrgr(hMcbsp0); /* Handle to SRGR ‘ */
switch (xfer_type) {
case DMA_AC97:
 
//#if (EDMA_SUPPORT) /* For EDMA supporting devices */
EDMA_clearPram(0x00000000); /* Clear PaRAM RAM of the EDMA */
set_interrupts_edma();
//#endif
/*???????????????????????????????????????????????????????????????????????????????*/
/* EDMA channels 12 and 13 config structures */
/*???????????????????????????????????????????????????????????????????????????????*/
//#if (EDMA_SUPPORT) /* for EDMA supporting devices */
hEdma1 = EDMA_open(EDMA_CHA_REVT0, EDMA_OPEN_RESET);
EDMA_configArgs(hEdma1,

//#if (C64_SUPPORT)
EDMA_OPT_RMK(
EDMA_OPT_PRI_HIGH, /* High priority EDMA */
EDMA_OPT_ESIZE_32BIT, /* Element size 32 bits */
EDMA_OPT_2DS_DEFAULT,
EDMA_OPT_SUM_DEFAULT,
EDMA_OPT_2DD_DEFAULT,
EDMA_OPT_DUM_INC, /* Destination increment by element size */
EDMA_OPT_TCINT_YES, /* Enable Transfer Complete Interrupt */
EDMA_OPT_TCC_OF(13), /* TCCINT = 0xD, REVT0 */
EDMA_OPT_TCCM_DEFAULT,
EDMA_OPT_ATCINT_DEFAULT,
EDMA_OPT_ATCC_DEFAULT,
EDMA_OPT_PDTS_DEFAULT,
EDMA_OPT_PDTD_DEFAULT,
EDMA_OPT_LINK_YES, /* Enable linking to NULL table */
EDMA_OPT_FS_NO
),
//#endif
EDMA_SRC_RMK(MCBSP_ADDRH(hMcbsp0, DRR)), /* src to DRR0 */
EDMA_CNT_RMK(0, frame_count * element_count),/* no. of elements */
/* Optionally replace the above with the following line */
/* EDMA_CNT_RMK(frame_count, element_count), */
EDMA_DST_RMK((Uint32)edmaInbuff), /* dst addr to edmaInbuff */
EDMA_IDX_RMK(0,0),
EDMA_RLD_RMK(0,0)
);
hEdma2 = EDMA_open(EDMA_CHA_XEVT0, EDMA_OPEN_RESET);
EDMA_configArgs(hEdma2,

//#if(C64_SUPPORT)
EDMA_OPT_RMK( /* For 64x devices only */
EDMA_OPT_PRI_HIGH, /* High priority EDMA */
EDMA_OPT_ESIZE_32BIT, /* Element size 32 bits */
EDMA_OPT_2DS_DEFAULT,
EDMA_OPT_SUM_INC, /* Source increment by element size */
EDMA_OPT_2DD_DEFAULT,
EDMA_OPT_DUM_DEFAULT,
EDMA_OPT_TCINT_YES, /* Enable Transfer Complete Interrupt */
EDMA_OPT_TCC_OF(12), /* TCCINT = 0xC, XEVT0 */
EDMA_OPT_TCCM_DEFAULT,
EDMA_OPT_ATCINT_DEFAULT,
EDMA_OPT_ATCC_DEFAULT,
EDMA_OPT_PDTS_DEFAULT,
EDMA_OPT_PDTD_DEFAULT,
EDMA_OPT_LINK_YES, /* Enable linking to NULL table */
EDMA_OPT_FS_NO
),
//#endif
EDMA_SRC_RMK((Uint32)edmaOutbuff), /*src to edmaOutbuff */
EDMA_CNT_RMK(0,frame_count * element_count), /* set no. of elements */
/* Optionally replace the above with the following line */
/* EDMA_CNT_RMK(frame_count, element_count), */
EDMA_DST_RMK(MCBSP_ADDRH(hMcbsp0, DXR)), /* dst addr to DXR0 */
EDMA_IDX_RMK(0,0),
EDMA_RLD_RMK(0,0)
);
hEdmadummy = EDMA_allocTable(?1); /* Dynamically allocates PaRAM RAM table */
EDMA_configArgs(hEdmadummy, /* Dummy or Terminating Table in PaRAM */
0x00000000, /* Terminate EDMA transfers by linking to */
0x00000000, /* this NULL table */
0x00000000,
0x00000000,
0x00000000,
0x00000000
);
EDMA_link(hEdma1, hEdmadummy); /* Link terminating event to the EDMA event */
EDMA_link(hEdma2, hEdmadummy);
EDMA_enableChannel(hEdma1); /* Enable EDMA channels */
EDMA_enableChannel(hEdma2);
//#endif /* end for EDMA supporting devices */
}
/* make sure TOUT0 was low for >++ 1 usec */
for (delay_count = 0 ; delay_count < 500 ; delay_count++);
TIMER_setDataOut(hTimer0,1); /* Write a 1 to the TOUT0 */
/* wait for BITCLK to start */
for (delay_count = 0 ; delay_count <100 ; delay_count++);
MCBSP_enableRcv(hMcbsp0); /* Enable McBSP channel */
MCBSP_enableXmt(hMcbsp0); /* McBSP port 0 as the transmitter/receiver */
MCBSP_enableFsync(hMcbsp0); /* Enable frame sync for the McBSP */

/* To flag an interrupt to the CPU when EDMA transfer/receive is done */
/* Transfer completion interrupt 12 and 13 set flag = 1 when set */
//#if (EDMA_SUPPORT)
while (!xmit0_done || !recv0_done);
//#endif
MCBSP_close(hMcbsp0); /* close McBSP port */
//#if (EDMA_SUPPPORT)
EDMA_close(hEdma1); /* close EDMA channels */
EDMA_close(hEdma2);
EDMA_close(hEdmadummy);
//#/endif
TIMER_close(hTimer0); /* close TIMER 0 */
} /* end main, progam ends here */
/*???????????????????????????????????????????????????????????????????????????????*/
/* init_mcbsp0_ac97() */
/*???????????????????????????????????????????????????????????????????????????????*/
/* MCBSP Config structure */
/* Setup the MCBSP_0 for transfers with the AC97 codec*/
void
init_mcbsp0_ac97(void)
{
MCBSP_Config mcbspCfg0 = {
//#if (EDMA_SUPPORT)
MCBSP_SPCR_RMK(
MCBSP_SPCR_FREE_DEFAULT, /* All fields in SPCR set to default values */
MCBSP_SPCR_SOFT_DEFAULT,
MCBSP_SPCR_FRST_DEFAULT,
MCBSP_SPCR_GRST_DEFAULT,
MCBSP_SPCR_XINTM_DEFAULT,
MCBSP_SPCR_XSYNCERR_DEFAULT,
MCBSP_SPCR_XRST_DEFAULT,
MCBSP_SPCR_DLB_DEFAULT,
MCBSP_SPCR_RJUST_DEFAULT,
MCBSP_SPCR_CLKSTP_DEFAULT,
MCBSP_SPCR_DXENA_DEFAULT,
MCBSP_SPCR_RINTM_DEFAULT,
MCBSP_SPCR_RSYNCERR_DEFAULT,
MCBSP_SPCR_RRST_DEFAULT
),
//#endif

//#if (EDMA_SUPPORT)
MCBSP_RCR_RMK(
MCBSP_RCR_RPHASE_DUAL, /* Dual phase receive frame */
MCBSP_RCR_RFRLEN2_OF(0xB), /* frame length =12 elements */
MCBSP_RCR_RWDLEN2_20BIT, /* receive elements = 20 bits*/
MCBSP_RCR_RCOMPAND_DEFAULT,
MCBSP_RCR_RFIG_DEFAULT,
MCBSP_RCR_RDATDLY_1BIT, /* 1?bit receive data delay */
MCBSP_RCR_RFRLEN1_OF(0x0), /* frame length of 1 element */
MCBSP_RCR_RWDLEN1_16BIT, /* receive elements = 16bits */
MCBSP_RCR_RWDREVRS_DEFAULT
),
//#endif

//#if (EDMA_SUPPORT)
MCBSP_XCR_RMK(
MCBSP_XCR_XPHASE_DUAL, /* Dual phase transmit frame */
MCBSP_XCR_XFRLEN2_OF(0xB), /* frame length =12 elements */
MCBSP_XCR_XWDLEN2_20BIT,
MCBSP_XCR_XCOMPAND_DEFAULT,
MCBSP_XCR_XFIG_DEFAULT,
MCBSP_XCR_XDATDLY_1BIT, /* 1?bit transmit data delay */
MCBSP_XCR_XFRLEN1_OF(0x0), /* frame length of 1 element */
MCBSP_XCR_XWDLEN1_16BIT, /* receive elements = 16bits */
MCBSP_XCR_XWDREVRS_DEFAULT
),
//#endif

MCBSP_SRGR_RMK(
MCBSP_SRGR_GSYNC_FREE, /* Free running driven by CLKS */
MCBSP_SRGR_CLKSP_DEFAULT,
MCBSP_SRGR_CLKSM_CLKS, /* External clock source, CLKS, deriv
CLKSM */
MCBSP_SRGR_FSGM_FSG, /* FSX driven by SRG frame sync signal */
MCBSP_SRGR_FPER_OF(0xFF), /* Frame period is 256 CLKS 12.288MHz
periods */
MCBSP_SRGR_FWID_OF(0xF), /* Frame sync signal width = 16 BITCLK */
MCBSP_SRGR_CLKGDV_OF(0) /* CLKG same freq. as SRGR input clock CLKS */
),
//#if (C64_SUPPORT)
MCBSP_MCR_RMK( /* only for 64x */
MCBSP_MCR_XMCME_DEFAULT, /* All fields in MCR set to default values */
MCBSP_MCR_XPBBLK_DEFAULT,
MCBSP_MCR_XPABLK_DEFAULT,
MCBSP_MCR_XMCM_DEFAULT,
MCBSP_MCR_RPBBLK_DEFAULT,
MCBSP_MCR_RMCME_DEFAULT,
MCBSP_MCR_RPABLK_DEFAULT,
MCBSP_MCR_RMCM_DEFAULT
),

//#if (C64_SUPPORT)
MCBSP_RCERE0_RMK(0), /* Additional registers only for 64x */
MCBSP_RCERE1_RMK(0),
MCBSP_RCERE2_RMK(0),
MCBSP_RCERE3_RMK(0),
//#endif
//#if (C64_SUPPORT)
MCBSP_XCERE0_RMK(0), /* Additional registers only for 64x */
MCBSP_XCERE1_RMK(0),
MCBSP_XCERE2_RMK(0),
MCBSP_XCERE3_RMK(0),
//#endif
MCBSP_PCR_RMK(
MCBSP_PCR_XIOEN_DEFAULT,
MCBSP_PCR_RIOEN_DEFAULT,
MCBSP_PCR_FSXM_INTERNAL, /* Frame sync generated internally */
MCBSP_PCR_FSRM_INTERNAL, /* Frame sync generated internally */
MCBSP_PCR_CLKXM_DEFAULT,
MCBSP_PCR_CLKRM_DEFAULT,
MCBSP_PCR_CLKSSTAT_DEFAULT,
MCBSP_PCR_DXSTAT_DEFAULT,
MCBSP_PCR_FSXP_ACTIVEHIGH, /* FSX is active high */
MCBSP_PCR_FSRP_ACTIVEHIGH, /* FSR is active high */
MCBSP_PCR_CLKXP_DEFAULT,
MCBSP_PCR_CLKRP_DEFAULT
)
};
hMcbsp0 = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); /* McBSP port 0 */
MCBSP_config(hMcbsp0, &mcbspCfg0);
}
/*???????????????????????????????????????????????????????????????????????????????*/
/* set_interrupts_edma() */
/*???????????????????????????????????????????????????????????????????????????????*/
//#if (EDMA_SUPPORT)
void /* Set the interrupts */
set_interrupts_edma(void) /* if the device supports EDMA */
{
IRQ_nmiEnable();
IRQ_globalEnable();
IRQ_reset(IRQ_EVT_EDMAINT);
IRQ_disable(IRQ_EVT_EDMAINT);
EDMA_intDisable(12); /* ch 12 for McBSP transmit event XEVT0 */
EDMA_intDisable(13); /* ch 13 for McBSP receive event REVT0 */
IRQ_clear(IRQ_EVT_EDMAINT);
EDMA_intClear(12);
EDMA_intClear(13);
IRQ_enable(IRQ_EVT_EDMAINT);
EDMA_intEnable(12);
EDMA_intEnable(13);
return;
}
//#endif
/*???????????????????????????????????????????????????????????????????????????????*/

/*???????????????????????????????????????????????????????????????????????????????*/
/*interrupt void
c_int11(void)
{
xmit0_done = TRUE;
return;
}
interrupt void
c_int09(void)
{
recv0_done = TRUE;
return;
}*/
interrupt void /* vecs.asm hooks this up to IRQ 08 */
c_int08(void) /* for the EDMA */
{
//#if (EDMA_SUPPORT)
if (EDMA_intTest(12))
{
xmit0_done = TRUE;
EDMA_intClear(12); /* clear CIPR bit so future interrupts can be recognized */
}
else if (EDMA_intTest(13))
{
recv0_done = TRUE;
EDMA_intClear(13); /* clear CIPR bit so future interrupts can be recognized */
}
//#endif
return;
}
/*???????????????????????End of ac97codec.c?????????????????????????????????????*/