module LFSR_10bits1(clk,nrst,random1);
 input clk;
 input nrst;
 output [9:0]random1;
 reg[9:0]random1;
 integer i;
 parameter taps=10'b1000111100;
 always@(posedge clk or negedge nrst)
 begin
  if(!nrst)random1<=10'b0000000001;
  else
  begin
   for(i=0;i<=8;i=i+1)
   if(taps[i])
 random1[i+1]<=random1[i]^random1[9];
   else
 random1[i+1]<=random1[i];
 random1[0]<=random1[9];
 end
end
endmodule

module LFSR_10bits2(clk,nrst,random2);
 input clk;
 input nrst;
 output [9:0]random2;
 reg[9:0]random2;
 integer i;
 parameter taps=10'b1000000001;
 always@(posedge clk or negedge nrst)
 begin
  if(!nrst)random2<=10'b0000000001;
  else
  begin
   for(i=0;i<=8;i=i+1)
   if(taps[i])
 random2[i+1]<=random2[i]^random2[9];
   else
 random2[i+1]<=random2[i];
 random2[0]<=random2[9];
 end
end
endmodule

module CA(clk,nrst,random);
 input clk;
 input nrst;
 output [9:0]random;
 reg[9:0]random;
 wire [9:0]a,b;
 always@(posedge clk)
  begin
  #2 random[0]<=a[0]^b[0];
  random[1]<=a[1]^b[1];
  random[2]<=a[2]^b[2];
  random[3]<=a[3]^b[3];
  random[4]<=a[4]^b[4];
  random[5]<=a[5]^b[5];
  random[6]<=a[6]^b[6];
  random[7]<=a[7]^b[7];
  random[8]<=a[8]^b[8];
  random[9]<=a[9]^b[9];
  end
 LFSR_10bits1 inst1(.clk(clk),.nrst(nrst),.random1(a));
 LFSR_10bits2 inst2(.clk(clk),.nrst(nrst),.random2(b));
endmodule

module test_CA();
 reg clk;
 reg nrst;
 wire [9:0]random;
 always#20 clk=!clk;
 initial
 begin
  #0 clk=0;
  #10 nrst=1;
  #20 nrst=0;
  #20 nrst=1;
 end
 CA inst(.clk(clk),.nrst(nrst),.random(random));
endmodule