术语“栅格”和“分辨率”的混淆和相互替换，对DSM（深亚微米）和亚波长半导体设计的生产、可靠性和制造，已经形成巨大的消极影响。

　　近来混淆两个截然不同术语的趋势，对DSM（深亚微米）和亚波长半导体设计的生产、可靠性和制造，已经形成巨大的消极影响。对于结构设计数据库，混淆和交换术语“栅格”和“分辨率”成为趋势。

　　分辨率涉及结构设计数据库存储的最小单元。对标准GDSII（图形设计系统II）流文件，米制设计的分辨率为0.001微米。相对比，栅格涉及版面设计师布版过程中排列目标的栅格最小斜度。栅格为分辨率的整数倍。此外，栅格大小与制造设计掩模的最小化电子束点大小成比例。在典型的130或90nm设计中，栅格典型为0.01微米——为分辨率的10倍。

　　大多数工艺流程设计规则文档指定工作栅格，确保与掩模生成过程兼容。固有的数据库分辨率通常未指明，且假定为GDSII或OASIS数据库。制造过程流程假定数据出现在设计栅格的所有边缘和高点。结果，信息传输到所有设计报告都提及的MDP（掩模数据准备）阶段。

　　历史上，版面工程师和那些熟悉全套设计规则的工程师开发了大多数制版工具。但现在

　　更悲惨的结果是当边缘不在栅格上时，DRC失败（设计规则检查）。查证和MDP程序将设计数据对齐到固有栅格，增加或减少印制板物体的宽度或间距。这个调整可以导致IC设计功能和运转的改变。

　　许多新型DFM（面向制造的设计）工具实现RET/OPC（分辨率增强技术/光学相位修正）应用，也假定栅格参数涉及掩模制造工艺，且与数据库的分辨率不同。例如，DFM工具通过移动设计的边缘和高点增加印制板间距。如果数据不在栅格——例如，栅格为0.01微米的整数倍，但器件位于0.014微米——间距改变也许不善改变解决间距问题。此外，当给设计增加新拐角走线或人造线时，它们位于掩模栅格上。当设计没有位于同一栅格上时，新OPC器件或者没有从现有结构延伸到全距离，或者没有在OPC器件和设计器件之间没有缺口。结果，这种情形极大地减少了OPC偏离栅格数据的改进。

　　对DSM的装配和最终发布及亚波长设计，整理IP，在MDP和RET相位设计前使其与掩模制造栅格兼容是重要的。IP的确认、定制模块和Pcell，必须完整地依从实际掩模转换的数据库，而不仅是设计的工作数据。

　　英文原文：

　　Grid and resolution: Defining two critical terms in IC design

　　Confusion and interchange of the terms "grid" and "resolution" has had a huge negative impact on the yield, reliability, and manufacturability of DSM (deep-submicron) and subwavelength semiconductor designs.

　　By Pallab Chatterjee, Contributing Technical Editor -- EDN, 12/3/2007

　　A recent trend confusing two quite different terms has had a huge negative impact on the yield, reliability, and manufacturability of DSM (deep-submicron) and subwavelength semiconductor designs. This trend is the confusion and interchange of the terms “grid” and “resolution” with respect to the physical-design database.

　　Resolution refers to the minimum database unit that the physical-design database stores. For a standard GDSII (Graphic Design System II) stream file, the resolution is 0.001 micron for metric designs. In contrast, grid refers to the minimum pitch of the grid where the layout designer aligns objects during placement. The grid is an integer multiple of the resolution. Additionally, the grid size is proportional to the minimum electron-beam-spot size used to create the masks for the design. On a typical 130- or 90-nm design, the grid is typically 0.01 micron—10 times the resolution.

Most process-design-rule documents specify the working grid to ensure compatibility with the mask-generation processing. The inherent database resolution is usually unspecified and assumed for the GDSII or OASIS (Open Artwork System Interchange Standard) database. The assumption of the manufacturing-process flow is that the data appears with all edges and vertices on the design grid. As a result, the information transfers to the MDP (mask-data-prep) stages with all the design information intact.

　　Historically, layout engineers and those familiar with the full set of design rules would set up most layout tools. But today, software developers lacking a complete understanding of the engineering requirements of the grid parameter are the ones who develop many of the technology files that vendors distribute as downloadable infrastructure. As a result, most of the custom-layout and IP (intellectual-property)-placement design-technology files have the grid parameter set equal to the resolution parameter at 0.001 micron. Redrawing and zooming time increases because of the fine resolution and the large number of objects you are assembling. This increase immediately impacts the parameter setting, reducing design throughput.

　　A more disastrous result is the failure of the DRC (design-rules checking) that occurs when edges are not on the grid. The verification and MDP routines snap the design data to the planned grid and either increase or decrease the width or the spacing of layout objects. This adjustment can result in a change of the IC design’s function and operation.

　　Many of the new DFM(design-for-manufacturing) tools implementing RET/OPC (resolution-enhancement-technology/optical-proximity-correction) applications also assume that the grid parameter relates to the mask-making process and differs from the resolution of the database. For example, DFM tools increase spacing on the layout by moving edges and vertices of the design. If the data is not on the grid—for example, the grid is a multiple of 0.01 micron but an object is at 0.014 micron—then spacing changes may not resu

　　For the assembly and final release of DSM and subwavelength designs, it is essential to clean up IP, making it compatible with the mask-making grid before the MDP and RET phase of the design. The verification of the IP, custom blocks, and Pcells must be complete for the grid compliance on the actual mask-transfer database, not just the working data of a design.