This article will discuss how the ASIC vendor can assist the OEM board design and FPGA design teams in "designing for portability," so that their strategies for power supplies, package types, I/O utilization, IP selection and the development of timing scripts and clocking architectures can be developed with consideration of maximizing cost reduction through conversion to ASIC. Additionally, it will discuss the strategies ASIC and structured ASIC designers should consider to assure first time success of their designs in silicon and a smooth transition from prototype approval to volume production of reliable, cost-effective devices.

No chip is an island
The old saying that "no man is an island unto himself" can be applied to electronic components also. No FPGA or ASIC has any practical function until it is connected to the broader environment of the program board and through that, to an overall system or piece of equipment. Yet it can happen that the mindset of the board-designer who develops component specifications and the FPGA or component designer who works to realize those specifications can be "insular" and focused on the task at hand, with little thought given to requirements of future cost reduction.

When such cost reduction efforts are initiated later – sometimes by other groups entirely – it is often the case that the program board and its components have gone through system qualification and are by that time "frozen," so that any replacement parts must be "footprint" as well as functionally identical. This can limit the opportunities of cost reduction an ASIC vendor can offer at that point.

By contrast, OEM board and component design teams that consider paths to eventual cost reduction early in the process, at the concept stage, can benefit by involving potential ASIC suppliers early in that process and keep them involved through completion of the board and component design phases. The advice that the ASIC vendor can offer will permit a smoother "portability" from the FPGA to a lower cost ASIC and will allow the vendor to take advantage of the most efficient design for cost reduction as regards technology, packaging and test methodology. Let's examine how this process can work.

Design for portability
Decisions made by program board and FPGA designers can impact the eventual conversion to a low cost ASIC either positively or negatively. By bringing the ASIC vendor into the process early, the ASIC vendor can assist in implementation of a "parallel design flow" (Fig 1), whereby RTL is developed and targeted to the FPGA which will also permit easy migration to an eventual ASIC. Timing scripts and clocking architectures are developed for both the FPGA and the ASIC.

1. Parallel design flow.

In general, the more synchronous the design, the more portable it is to other technology nodes. Certain design practices regarding the avoidance of gated clocks and synchronization of data transfers between clock domains can greatly enhance the portability of the FPGA to the ASIC.

Many FPGAs deliver faster clock-to-out times than are required by system performance. If the FPGA designer can document the system clock-to-out requirements for the ASIC conversion, an ASIC technology that is older than the FPGA technology may be considered, resulting in additional cost savings due to the reduced cost of silicon. Additionally, the ASIC designer may be able to reduce the I/O currents and improve board-level signal integrity.

In selecting IP for the FPGA, it is recommended to either use third-party party "soft" I/P that's portable to other technologies or to use IP supplied by the ASIC vendor (which can be more easily ported to the eventual ASIC, thus making the design as "technology independent" as possible. Using certain customized FPGA IP may impede or even prevent conversion to an ASIC.

The program board can be developed with consideration of both the large, power-hungry FPGA package and a smaller, more efficient package for the eventual ASIC (Fig 2). FPGAs use more power than an ASIC and require a higher performance package, whereas the ASIC can often utilize a lower performance industry standard package with fewer pins or ball counts and thus reduced cost.

2. Package shrink.

Additionally, the program board can be designed with an isolated power supply for the FPGA core allowing a regulator or resistor change to switch to a higher core voltage for the ASIC that may be manufactured in a less expensive technology than the FPGA.

JTAG implementation at the board level may take into consideration only the FPGA I/O that are actually utilized and which would be required for functional implementation in the corresponding cost-reduced ASIC. Otherwise, the ASIC die size (and cost) may need to grow to support all the unused I/O of the FPGA.
Finally, with the ASIC vendor involved early in the board and FPGA design process, it is possible for the vendor to evaluate the FPGA netlist prior to its being finalized and do early debug of any issues that would make portability to an ASIC problematic, so that these can be addressed before the FPGA code is "frozen" and the board is qualified. The resulting ASIC has the best chance of providing maximum cost reduction by minimizing die size and utilizing the most cost effective technology and packaging – in effect, the most suitable manufacturing practices.

Continuous improvement in manufacturability of ASIC designs
In addition to assisting the OEM board development and FPGA design teams early in the design process, ASIC vendors who supply conversion services must also adopt a "continuous improvement" strategy to make their design practices more robust, eliminate systematic errors, increase the chances for "first time success" in silicon, transfer their products from design to manufacturing as quickly as possible, and reduce the possibility of customer returns for reliability issues. The old-school practice of "tossing a new design over the wall" to manufacturing has long been replaced by increasing consideration of the requirements of manufacturing at all phases of ASIC design. Some cases in point are as follows:

• Structured Arrays: Certain ASIC conversion vendors offer some form of structured array to reduce the cost of design in time and tooling by utilizing standardized design elements, memory blocks, I/O structures in the base layers and only programming the top levels. These products target the advanced FPGAs in their performance characteristics and may also reduce die size by utilizing an RDL structure for surface bonding into flip-chip packages. The benefit in manufacturing is that when running in volume new orders can be built from a mid-line wafer stockroom, thus reducing manufacturing leadtime as well.
   
  
• Design Technology Partnerships: Although some ASIC conversion vendors have in-house wafer fab available, for leading edge process technologies ,a partnership with a leading foundry is a key design/product strategy. Since ASIC conversions assume a product life of three to five years or more, factors such as process lifetime support, availability of libraries and IP may be more important factors than the cost of silicon in selecting a partner.
   
  
• Designing in 'Nano' Processes: Designers doing FPGA conversions into sub-180 nano process technologies need to be sensitive to the physics of that environment and its implications for power and leakage, power pad requirements and the resulting effect on total pads and die size. The available capacity and minimum volume order rules of technology partners (fabs) should also be reviewed.
   
  
• Design Methodologies: As FPGAs become larger and increasingly complex, the design flow for managing FPGA-to-ASIC conversions necessarily expands on the front-end to include more up-front evaluation of early customer netlists/RTL prior to receiving the final, fixed netlist. This early involvement may include a trial layout and simulation to detect problems that can still be resolved by the FPGA design team. The use of design checklists and a detailed project plan at kick-off improves the chance of first time success in silicon by confirming the customer specification and catching design violations, errors and bad practices earlier in the process.
   
  
• Design For Test (DFT): Continuous improvement in DFT methodology increases the fault coverage assured through a combination of Iddq testing, SCAN, Boundary SCAN (JTAG) and memory Built-in-Self Test (BIST) in addition to parametric and functional tests to achieve tighter quality and reliability targets in the 100ppm range and below. Also, ASIC vendors tend to target industry standard, widely available tester platforms that are supported by the major test subcontractors to have the benefit of flexibility of moving test programs quickly when necessary.
   
  
• Targeting Industry Standard Packages: To the extent made possible by customer requirements, vendors of ASIC conversion services will attempt to target high volume industry standard packages in preference to more exotic, "one-of" or custom packages to get the benefit in cost that comes from volume. They must also be sensitive to trends in package supply as the major packaging houses and the suppliers of molding compound and leadframes determine availability and cost. Lastly, for drop-in replacement, many FPGA conversions require that a custom package is developed. The supplier needs to have expertise in this area to assure drop-in replacement works the first time between the FPGA and ASIC.
   
  
• ESD Protection and Moisture Protection: Over the past five years, continuous improvement in Electrostatic Discharge (ESD) protection at the design level has increased the quality and reliability of product from many ASIC vendors. In response to industry data about field failures related to ESD and moisture sensitivity, designers now incorporate protective structures in I/O cells to achieve industry expectations and to utilize dessicant packing bags and ESD protected packing boxes for shipment of IC's.

Conclusion
ASIC vendors and providers of FPGA-to-ASIC conversion services utilize a variety of design practices and strategies to achieve "first time success" in silicon, leverage the cost reduction potential of volume manufacturing, improve yields and reduce customer returns based on quality. They also have much to offer OEM design teams in the early phases of program board and FPGA design, if permitted to give input to that process in anticipation of an eventual conversion of an FPGA to an ASIC for cost reduction.