| EP2C5汽车电子图像系统设计（Altera） |
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| 作者：未知 来源：本站原创 点击数：231 更新时间：2008-3-13 |
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Altera 公司的EP2C5是Cyclone II FPGA系列器件，具有4068个LE和26个M4K嵌入RAM区块，有13个乘法器，支持Nios II嵌入处理器，可以实现低成本高性能的嵌入式处理解决方案。本文介绍Cyclone II EP2C5的主要性能以及在汽车电子图像系统中的应用和汽车电子图像系统参考设计方框图。
Automotive Graphics Controller Reference Design
1．Cyclone II FPGA性能介绍
Altera® Cyclone II FPGAs extend the low-cost FPGA density range to 68,416 logic elements (LEs) and provide up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are manufactured on 300-mm wafers using TSMCs 90-nm low-k dielectric process to ensure rapid availability and low cost. By minimizing silicon
area, Cyclone II devices can support complex digital systems on a single chip at a cost that rivals that of ASICs.
Cyclone II devices support the Nios II embedded processor which allows you to implement custom-fit embedded processing solutions. Cyclone II devices can also expand the peripheral set, memory, I/O, or performance of embedded processors. Single or multiple Nios II embedded processors can be designed into a Cyclone II device to provide additional co-processing power or even replace existing embedded processors in your system. Using Cyclone II and Nios II together allow for low-cost,
high-performance embedded processing solutions which allow you to extend your products life cycle and improve time to market over standard product solutions.
The Cyclone II device family offers the following features:
■ High-density architecture with 4,608 to 68,416 LEs
● M4K embedded memory blocks
● Up to 1.1 Mbits of RAM available without reducing available logic
● 4,096 memory bits per block (4,608 bits per block including 512 parity bits)
● Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
● True dual-port (one read and one write, two reads, or two writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes
● Byte enables for data input masking during writes
● Up to 260-MHz operation
■ Embedded multipliers
● Up to 150 18- × 18-bit multipliers are each configurable as two independent 9- × 9-bit multipliers with up to 250-MHz performance
● Optional input and output registers
■ Advanced I/O support
● High-speed differential I/O standard support, including LVDS, RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL
● Single-ended I/O standard support, including 2.5-V and 1.8-V, SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-, and 1.8-V LVTTL
● Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V operation at 33 or 66 MHz for 32- or 64-bit interfaces
● PCI Express with an external TI PHY and an Altera PCI Express
×1 Megacore® function
● 133-MHz PCI-X 1.0 specification compatibility
● High-speed external memory support, including DDR, DDR2, and SDR SDRAM, and QDRII SRAM supported by drop in Altera IP MegaCore functions for ease of use
● Three dedicated registers per I/O element (IOE): one input register, one output register, and one output-enable register
● Programmable bus-hold feature
● Programmable output drive strength feature
● Programmable delays from the pin to the IOE or logic array
● I/O bank grouping for unique VCCIO and/or VREF bank settings
● MultiVolt™ I/O standard support for 1.5-, 1.8-, 2.5-, and 3.3-interfaces
● Hot-socketing operation support
● Tri-state with weak pull-up on I/O pins before and during configuration
● Programmable open-drain outputs
● Series on-chip termination support
■ Flexible clock management circuitry
● Hierarchical clock network for up to 402.5-MHz performance
● Up to four PLLs per device provide clock multiplication and division, phase shifting, programmable duty cycle, and external clock outputs, allowing system-level clock management and skew control
● Up to 16 global clock lines in the global clock network that drive throughout the entire device
■ Device configuration
● Fast serial configuration allows configuration times less than 100 ms
● Decompression feature allows for smaller programming file storage and faster configuration times
● Supports multiple configuration modes: active serial, passive serial, and JTAG-based configuration
● Supports configuration through low-cost serial configuration devices
● Device configuration supports multiple voltages (either 3.3, 2.5, or 1.8 V)
■ Intellectual property
● Altera megafunction and Altera MegaCore function support, and Altera Megafunctions Partners Program (AMPPSM) megafunction support, for a wide range of embedded
processors, on-chip and off-chip interfaces, peripheral functions, DSP functions, and communications functions and protocols.
● Nios II Embedded Processor support
2．汽车电子图像系统参考设计
The Automotive Graphics System reference design demonstrates the use of Altera Cyclone® FPGAs in a graphics system targeted at the Automotive sector. This reference design shows the power and flexibility available in FPGAs for targeting low-cost applications such as those required by the Automotive marketplace.
主要性能：
The main features of this reference design are:
Video input hardware module.
Clipping
Color space conversion
Horizontal and vertical scaling
TFT display controller
5-layer display
Picture in picture
Graphics library running on Nios®II processor
Runs on Nios II Cyclone development board
Lancelot VGA video controller required
SDRAM program store and frame buffer
图1。汽车电子图像系统参考设计方框图
图2。采用Cyclone II EP2C5 FPGA实现的低成本图像[1]
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