| Amphion MPEG-2视频译码器解决方案(CS6651) |
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| 作者：Amphion 来源：21IC中国电子网 点击数：149 更新时间：2008-3-18 |
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A high-performance solution for a broad range of image applications, the CS6651 is designed for standard definition video, is compliant with the ISO/IEC 13818-2 standard, and capable of decoding video streams at the MP@ML standard.
Features(特性)
Supports progressive scan and interlaced streams
ISO/IEC 13818-2 (H.262)-compliant
Main profile at main level (MP@ML) compliant
Decodes ISO/IEC11172-2 (MPEG1)
Constrained parameter bitstreams
High-performance solution for MPEG2 decoding
Supports input bit rates up to 30 Mbps
Real time decode and display of MP@ML using a single 27-MHz clock
Supports PAL and NTSC standard definition television (SDTV) resolutions and frame rates
Bitstream error detection and recovery
Glueless interface to external SDRAM
Capable of standalone stream decoding or host CPU-controlled operation
Fully synchronous design with host shutdown and restart control
Block Diagram(方框图)
Figure 1 shows the block diagram for the digital video broadcast (DVB) forward error correction (FEC) codec megafunction.
Figure 1. Block Diagram
Description(MPEG-2译码器描述)
The CS6651 MPEG-2 decoder provides high-performance solutions for a broad range of motion image applications. This highly-integrated semiconductor intellectual property (IP), designed for standard definition video, is compliant with the ISO/IEC 13818-2 standard (MPEG-2), and is capable of decoding video streams at the MP@ML standard. The CS6651 is at home in mainstream consumer applications and can also decode MPEG-1 (ISO/IEC 11172-2) bitstreams.
The CS6651 accepts the input video elementary stream as aligned bytes from conditional access decryption, transport stream demultiplexer, or a similar source. The maximum average input bit rate is 30 Mbps. The core can operate in a default mode on an input stream without the intervention of a host CPU. In this mode, pictures will be decoded from the video stream and output in the correct display order. A host CPU has access to a full range of information and control to manipulate the behavior of the decoder to permit audio/video synchronization, pan-and-scan and letterbox conversion, and various trick modes. A highly configurable pixel stream direct memory access (DMA) engine provides the output from the core. This engine allows adjustable output video component sequencing and provides external logic with control over the display of the picture. To meet the bandwidth requirements of MP@ML decoding, a dedicated SDRAM chip is used. This is a commodity 64-Mbit SDRAM in 2M- by 32-bit configuration.
Applications for the CS6651 include:
Digital cable and satellite set-top decoder box for SDTV
DVD players
PC video hardware accelerator
Device Utilization Example
Table 1列出用于MPEG-2译码器的Altera公司的器件
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