Introduction
Embedded design in Verilog using FPGAs can utilize controller and datapath modules to facilitate the implementation of real-time tasks. The controller module accepts external control and status signals from the datapath module and uses one or more finite state machines (FSM) to coordinate the process. The controller module provides the datapath module control input signals that route the input data, perform processing and output the data. The datapath module stores and manipulates data in registers using combinational and sequential logic and can use one or more FSMs to output the data but not autonomously. The controller can also accept external control signals from and return status signals to an external processor or internal soft core processor to augment the performance of the embedded system.

The controller and datapath construct partitions the design into modules that can be separately verified in simulation. Rather than one module that encapsulates the entire process, the controller and datapath modules then each have a reduced number of interconnections which facilitates the Verilog structural and behavioral synthesis into FPGA hardware. Datapath modules also support the concept of design reuse.

The controller module can be easily modified to accommodate a new task, which can then even include additional datapath modules. The configuration of a typical controller and datapath construct is shown in Fig 1. The synchronous clock input schedules the state transitions of the FSMs of the controller and datapath. Registers can be initialized by a global reset signal, a local reset signal or by a declaration in the behavioral synthesis of the controller and datapath. The reset signal is not shown in Fig 1.

1. Configuration of a typical controller and datapath construct.

The controller has control input logic signals that initiate the process and status output logic signals that signify the completion of the process. The datapath has only data as an input and output and no external process control logic signals other than those derived from the controller. The datapath outputs status logic signals to the controller to coordinate the process. A clock signal is used to provisionally evoke a state transition in the FSM if utilized in the controller and datapath. The controller control signals and the datapath status signals are required to have a state transition.

DSP System
The DSP system consisting of an ADC, FPGA and DAC is shown in Fig 2. The ADC provides n-bit data to the FPGA and receives an a-bit data packet for command and control. The DAC receives both m-bit data and a d-bit data packet for command and control from the FPGA. A crystal oscillator provides a clock signal to the FPGA for synchronization and timing of the data transfers and to establish the sampling rate f_s of the DSP system.

2. DSP embedded hardware system.

This DSP system executes on the Xilinx Spartan-3E Starter Board using Verilog structural and behavioral synthesis modules that are developed using the Xilinx ISE tools. The Verilog modules are configured as FSMs and the controller and datapath construct. The DSP system is initially implemented as a straight-through processor that inputs and outputs an analog signal without any manipulation to assess the maximum data throughput rate with the Verilog top module s3eadcdac.v in Listing 1. The five Verilog modules operate in parallel in the top module.

Listing 1. ADC-DAC system top module for the
Xilinx Spartan-3E starter board.
(Click this image to view a larger, more detailed version)

The Verilog top module utilizes the se3adc.v and se3progamp.v modules for the ADC and programmable gain amplifier (PGA) and the se3dac.v and dacs3edcm.v modules for the DAC and the Digital Clock Manager (DCM) of the Xilinx Spartan-3E Starter Board. The DCM is an available Xilinx Architecture Wizard module which facilitates the embedded design. These four Verilog modules are FSM controllers for the ADC, PGA and DAC external peripherals and the soft-core peripheral DCM and are described in the text.

An output pin of one of the 6-pin peripheral ports is used to monitor the ADC conversion command signal (conad) and the sampling rate f_s = approximately 282 ksamples/sec here. This maximum sampling rate is far below the cutoff frequency of the anti-aliasing filter of the Spartan-3E Starter Board ADC (1.54 MHz). To avoid aliasing, an analog filter with a cutoff frequency f_cutoff < f_s/2 or f_cutoff < 141 kHz would have been appropriate.

Although data from the two ADC channels are available simultaneously, the DAC can only accept one channel of data at this sampling rate. In addition, the Xilinx Spartan-3E Starter Board DAC shares access to the serial peripheral interface (SPI) bus with the ADC (and other external peripherals) which leads to SPI bus contention and an even lower sampling rate.

The Xilinx Spartan-3E Starter Board ADC outputs 14-bit two's complement binary data and the DAC requires 12-bit straight binary data. The conversion is accomplished by complementing the MSB of the ADC output (bit 13) as the sign bit. The twelve MSBs of the ADC output (bit 13 through bit 2) are outputted to the DAC. Since the PGA inverts the analog input signal, the resulting straight binary data is complemented for comparison of the analog input and output signals on an oscilloscope.

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