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Design readiness enables companies to respond quickly to design needs, but how can its true cost be determined? And which solutions – Full Custom ASIC, FPGA, or Structured ASIC – are optimal for a given situation?
Although management and marketing often dictate that the engineering design department must be flexible and responsive, measuring the flexibility of a department is illusive at best. One way to start is by creating a valid metric for design response time, which can be used to help evaluate potential improvements and determine which ones are effective.
For example, is it important to be one day, one week, or one month earlier to market? The answer would seem to be an obvious "yes," and without the context of cost it would be an easy decision. But how much would it cost to shave off a few days from engineering design response time, and would that be that a good investment? Under certain circumstances, in low- and medium-volume situations, it is possible over the lifetime of a design to reduce the time to market and/or production time without incurring additional costs.
ViASIC, which makes EDA software for via-configurable Structured ASIC solutions, and Sandia National Labs have performed similar analysis to determine the cost of "design readiness." The results are particularly decisive because of the added time in the critical production path attributed to radiation and other harsh environment qualification. This analysis enables measured decisions regarding the cost of design readiness in full custom ASIC solutions, FPGAs, or structured ASIC solutions.
Of course, the engineering department might get concerned about terms like "investment" and "time-to-market." It sounds like business and management concepts are creeping into the engineering domain, and an analogy to mixing oil and water comes to mind ... but it is possible to get both on a salad if you shake them vigorously enough and pour quickly.
For the purposes of discussion, the first step is to create a quick reference metric that will help evaluate potential improvements in response times and flexibility, but it should be limited to the objectives of the engineering department. If our metric demonstrates opportunities to reduce the time it takes to implement an idea without increasing the cost, we would likely take those opportunities. For other cases, if we can quantify the cost increase for this response time reduction, marketing and management can provide their input to decide if it is a worthwhile opportunity to pursue.
The next step is to model these costs. This model is not intended to be comprehensive, but rather to provide a framework for companies to create a version applicable to their own decisions. The numbers we use are obviously contrived, though not completely unrealistic. We know from experience that one size does not fit all, that different situations call for different solutions, and that our model should reflect that outcome.
With any model, we need inputs. Time for production is the most important input because it is the cost of that time that we want to quantify. Part costs (marginal costs), and non-recurring costs (NRE or fixed costs) are obvious inputs, but we also need a projection of the number of parts to be produced. Fig 1 examines an FPGA solution, a Full Custom ASIC solution, and a Structured ASIC solution.
1. Relative cost per day of design response improvement.
Regarding part costs, the FPGA analysis is fairly straightforward, generally piece costs and shipping. The full custom ASIC analysis contains a few more components. As shown in Fig 1, piece costs must also include testing and packaging, although the piece cost is expected to be less.
Non-recurring costs must include mask charges and engineering charges specific to the ASIC solution. Tool costs are an ambiguous point to consider and depend on the specific engineering department. If the tools are already available, this might be considered a sunk cost. Certainly, any design efforts will add to the tool load, but the costs for this can vary greatly. We have inserted a guess for this number, but companies will need to create a version of this model specific to their situations.
Another major point regarding NRE is that it does NOT include the costs of the design itself, which are common across any of the options. Only NRE charges specific to a particular solution should be included. For instance, scan insertion might need to be done on the Custom ASIC or Structured ASIC, but not on the FPGA. The NRE for a structured solution is higher than that of an FPGA because of things such as test insertion, but it is less than a full custom solution because placement, routing, DRC, and LVS are simplified.
The number of parts required also will vary according to the situation, but this is a linear component of the model and the primary element that causes the model to produce a different result. Because some costs are not dependent on volume (NRE) and others are, this number should drive the linear portions of the model. Design life is used to determine the length of time across which the fixed costs should be amortized.
Production time is an interesting input, not so much from the standpoint of FPGA and ASIC choices, but it becomes more important as we add other alternatives. Anything in the critical path should be considered in this input. For commercial ASICs, this would include placement and routing above and beyond the FPGA requirements, mask generation, manufacturing, packaging, and test. For the FPGA solution, this would include programming, but also hidden time increases such as extra effort for design partitioning, or timing closure problems that occur due to performance limitations. The timeframe for the Structured ASIC solution (14 days) is based on the recent achievements of ViASIC and Sandia. The timeframe for the full custom ASIC is based on 12 weeks of production time. This is actually much greater if radiation effects must be qualified after manufacturing.
The model is simple and can be used to generate countless graphs and linear model analysis, and companies are invited to use it in their own situations. The equations are as follows:
- Total Cost = Design Life * Pieces per year * Piece cost + NRE
- Additional Cost = Max(Total Cost for each solution) – Total Cost
- Design Response Reduction = Max(Critical Path for each solution) – Critical Path
- Reduction Cost Per Day = Additional Cost / Design Response Reduction
Of course, we expect that the fastest response time and flexibility would be the most expensive. Throwing money at the problem will often work, but may not be the most desirable solution. As seen in Fig 1, removing that last 13 days can be expensive if FPGA solutions are used.
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