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One way that silicon suppliers reduce manufacturing costs is by discontinuing older product portfolios leading to microprocessor obsolescence. Multiple versions of those processor cores and a mix of integrated peripherals complicate the situation, leading to a plethora of silicon incarnations for each particular processor architecture.
By integrating peripherals into a single die with a microprocessor, the supplier could target the microcontroller to a particular application domain with high volume needs. (Throughout this article, the term "microcontroller" refers to the entire component, including the processor core and integrated peripherals.)
As applications and the standards by which they operate evolve over time, the narrower market space of the microcontroller design makes it more vulnerable to obsolescence. This article examines the options that are available to designers facing microprocessor (and microcontroller) obsolescence using FPGAs.
Before considering those options, however, it is helpful first to consider FPGA technology as a means to address the challenge of microprocessor obsolescence. On a LatticeXP2 FPGA, for example, the CPU core of a 68HC11 compatible can be implemented as fully synthesizable code in just 2600 slices. Implementing all the peripherals integrated on this component – as illustrated in the 68HC11 compatible microcontroller shown in Fig 1 – will increase this by a few hundred slices.
1. D68HC11 microcontroller implementation.
In addition to easily fitting onto today's FPGAs, this implementation can run, if desired, up to 5 times faster than the original 8-12 MHz component.
The technology curve
FPGAs let designers take advantage of the technology curve while protecting their designs from microprocessor obsolescence. The peripherals, or some combination of them, may also be in danger of obsolescence.
In addition to handling obsolete microcontrollers, the FPGA technology curve provides options for integrating surrounding functionality onto the FPGA and so reduces the overall system cost and eliminates concern over other components that may be discontinued.
While both SoC-based microcontrollers and FPGAs follow a technology curve as illustrated in Fig 2, with synthesizable RTL and FPGAs designers are protected from future obsolescence, not to mention the huge NREs associated with ASICs.
2. Technology curve adds integration headroom.
The technology curve graph in Fig 2 demonstrates the relative equivalent logic complexity of microprocessors and microcontrollers implemented in silicon versus a soft implementation in an FPGA. As we see, at the time the original microcontroller becomes obsolete, available FPGA logic density is much greater than what is required to implement the microprocessor and its peripherals.
This additional logic, called Peripheral Integration Headroom, will only grow with time as FPGA densities continue to increase. Indeed, the D86HC11 illustrated in Fig 1 includes the DoCD block, which provides real time, non intrusive system debugging; a function not originally integrated into the original microcontroller.
FPGAs offer a range of design trade-offs, so the designer is given choices in implementing a solution. Designers have the following options:
- Option 1: Complete redesign (and "future-proof" the design)
In this scenario, the device supplier might offer a replacement component that may or may not be a similar instruction set architecture (ISA). Choosing this option will require a complete redesign of the hardware and software, using either another component-based microcontroller solution or an FPGA-based solution. If this route is chosen, it is the perfect time to "future-proof" the design with an open source soft processor such as the 32-bit, Harvard architecture LatticeMico32. Unlike the GNU General Public License (GPL) with which the software community is familiar, the innovative open source license for the LatticeMico32 is hardware implementation friendly. It may be ported to any FPGA or ASIC free of charge.
- Option 2: Same ISA, Higher Integration
A soft implementation of the original microcontroller component (µP core and integrated peripherals) is programmed onto an FPGA. The soft processor implementation and/or its peripherals may run at a higher speed than in the original component. With this option, the software may require only the minor changes associated with any changes in the peripherals or timing loops. The benefits of this option are that software changes are minimized and the cost of the board is reduced, since other board functions are now integrated into the FPGA.
- Option 3: Binary Compatibility, Higher Integration
A soft implementation of the original microcontroller component (µP core and integrated peripherals) with cycle exact timing is programmed onto an FPGA. The goal here is to use the original binary code without modification. This option enables cost reduction of the board by integrating other original board functionality into the FPGA.
- Option 4: Binary Compatibility, Socket Compatibility (typical scenario)
This option uses a mezzanine board to implement the FPGA and minimal associated logic as an exact pin-for-pin replacement for the original microcontroller. This approach eliminates both software and hardware changes, except for the mezzanine board itself.
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