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Life used to be easy. If you were working on a multi-processor signal processing application, you would write down the requirements, check the specs of the devices on offer from the major DSP vendors, and just pick the chip that suited best.
Times have changed, and today's engineers are blessed with far more choice. The big FPGA vendors have stepped up their offerings for signal processing, and choosing the best solution can seem complex.
For distributed applications, the choice of interconnect technology can also obviously have a crucial effect on the overall solution. Crunching the data is all very well, but your system needs to have the right interfaces to move it around between the different processors, and off-load the results. What do the DSP and FPGA vendors have to offer in this area?
In this article, we'll look at what's available for multi-processor systems (which inevitably tends to mean the high-performance end of the market), and how you can make the best choice between DSP, FPGA or a hybrid mixture of the two. We'll look fairly briefly at issues involved in the two types of chip, but concentrate more on system-level factors.
For high-performance signal processing applications, of course there are other options beyond DSPs and FPGAs. Massively parallel processors from vendors like picoChip are one alternative, but unfortunately often require the use of the vendor's proprietary toolset. (See Analysis: BDTI benchmarks picoChip PC102.) ASICs and ASSPs are also well-suited to certain signal processing tasks, but their high up-front costs rule them out except in high volume applications.
DSPs evaluated
Pretty much since their invention in the 1980s, DSPs have provided excellent performance at reasonable power and cost levels. A large community of experienced DSP engineers has also grown alongside the technology, developing a substantial base of off-the-shelf field proven code to run on the DSP cores. There is also well-established support from third party vendors for debug and optimisation tools.
High performance DSPs continue to develop with faster clock speeds and multi-core solutions. Very-long instruction word (VLIW) DSPs provide high clock rates and independent execution units to get the maximum speed.
DSP development cost is relatively low, and as a mature technology it can be argued that it has a lower risk and faster time-to-market than FPGAs and other signal processing technologies.
DSPs can be attractive for many applications which are based on emerging standards, which often change frequently and rapidly. As DSP algorithms can be readily implemented in an accessible language such as C, it is easier to update the code to reflect changes in the standards as they occur. In addition, the complex nature of many of the signal processing algorithms in applications such as the latest wireless standards often make them more suitable to implement using a DSP: it is much easier for a DSP device to change the processing algorithm on-the-fly by calling a different software routine. While modern FPGAs can be reconfigured quickly, to achieve this dynamically while continuing to process data is a complex and challenging task.
DSPs are also improving their performance in the field of power. Led by the demands of the hand-held market, some next generation high-performance DSPs are incorporating power management techniques from their little brothers. This allows overall system power dissipation to be reduced during times of low traffic or to prevent over-temperature. A power and temperature-aware FPGA configuration could, of course, manage its clock domains in a similar way, but at the cost of greater development effort.
However, the DSP is not particularly well suited to parallel processing tasks: multiple devices can be required for tasks which easily fit into a single FPGA. For example, in wireless baseband applications, for the processing of WiMAX Orthogonal Frequency Division Multiple Access (OFDMA) channels, a pure DSP solution cannot match an FPGA in the bandwidth and number of channels it can process. Consequently the DSP solution may have an unacceptable cost and power per channel.
To improve DSP performance in specific algorithms, vendors have introduced hardware cores to handle some processing traditionally off-loaded to FPGAs. For example TI's TCI6482 DSP includes Viterbi and turbo decoder co-processors for 3GPP and 3GPP2, while the multi-core TCI6487 DSP also includes a direct Common Public Radio Interface (CPRI) / Open Base Station Architecture Initiative (OBSAI) interface which can be chained between DSPs.
The FPGA alternative
FPGAs have one big advantage over DSPs: their efficiency in concurrent applications, achieved by using multiple parallel processing blocks. Coupled with their flexibility to allow the embedded systems designer to tailor the device to match their application's demands as closely as possible, FPGAs can achieve the highest possible throughput with low cost per channel.
The FPGAs' flexibility has traditionally come with an additional cost in power due to the increased gate count and silicon area of non-optimised solutions in comparison to hard-wired architectures. However, 65-nm technologies and the use of equivalent ASIC technology for volume manufacture mean that FPGAs can be low-power in the lab, and power-reduced further in volume.
The per-channel power of an FPGA may now be well be below that of DSPs, even though the chip-level power dissipation is higher. DSPs typically consume 3-4W and FPGAs 7-10W but FPGAs can handle 10 times the channel density.
Acknowledging the advantages of DSPs has seen a shift in recent years to FPGAs incorporating DSP technology, for example Xilnx Virtex-5 SXT devices. This enables the FPGA to incorporate DSP algorithmic processing for tasks which are not naturally parallel. Such "DSP-enabled" FPGAs have shown huge throughput advantages for certain types of signal processing, which has been reflected in their success in the high-end processing market. However, FPGAs are in general ill-suited to processing sequential conditional data flow.
Programming FPGAs remains difficult, usually requiring a hardware-oriented language such as Verilog or VHDL. FPGA solutions can take an order of magnitude longer to code than DSP solutions which impacts development costs and increases time to market.
C-based synthesis tools have yet to deliver the ease of use and performance of C-coded processor solutions. High-level representations such as Simulink block diagram synthesis are not currently widely adopted and old FPGA synthesis methods still persist, especially where maximum performance is required.
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