Engineering students at the PSG College of Technology, Coimbatore, have proposed techniques that they say would enable design of highly power-efficient DSPs and other processors. The proposals include a new adder design and a method for implementing the multiplier circuit using decomposition logic.

In a paper presented at a recent VLSI design meeting here, Sundeepkumar Agarwal, V.K. Pavankumar and R. Yokesh described a full adder structure based on complementary pass transistor logic (CPL), mainly comprising NMOS transistors with pull-up PMOS transistors to obtain full-swing output voltage. They claim the structure is faster and more energy-efficient than existing adders.

"Due to positive feedback and the use of NMOS transistors, the circuit is inherently fast, and this property is utilized to reduce the width of the transistors in order to reduce power consumption without much speed degradation," the paper states. "The proposed adder has a balanced structure with respect to the generation of 'sum' and 'carryout' signals. This helps in the simultaneous arrival of signals in tree-structured circuits and thus reduces the generation of unwanted glitches."

The design uses a larger number of transistors than other approaches because it requires seven inverters to generate the complementary signals. "However, when this adder is used in designs such as a multiplier, the input complementary signals can be derived from previous stage outputs. This reduces the number of transistors," the authors state. "Also, the drivability of this adder is fairly good, even without the use of inverters. This is due to use of pullup PMOS transistors.

"Hence, the output inverters can be used in alternate stages of the design. As an example, in the design of a 4-bit ripple carry adder, the second and fourth full adders do not use output inverters for carry generation. [As a result,] one inverter delay is eliminated for every two full adders in the adder chain, and four transistors are reduced. Similarly, in complex designs like the multiplier, the output inverters for generating sum and carry can be used in alternative stages, thereby improving speed and reducing area."

Multiplier design

To improve the performance of multiplier structures—a core component of most DSPs—the authors propose a technique that leverages decomposition logic. They claim the approach both speeds operation and cuts power consumption by reducing spurious transitions on internal nodes.

In their proposed method to implement digital multipliers using decomposition logic, the multiplication process is split into subunits (smaller multipliers), and their outputs are combined to get the final results. In doing so, parallel processing is enabled, in addition to the benefits that accrue from tree-structured implementation of the multiplier.

For an 8 x 8 multiplier implemented using the decomposition logic, the researchers used four 4 x 4 multipliers in the first stage to combine all the partial products. The outputs from those 4 x 4 multipliers were combined to get the final results. An existing tree structure, the well-known fast multiplier proposed in the Wallace method, was used in the experiment.

The decomposition logic needs extra circuitry to perform the final addition of outputs from the 4 x 4 multipliers, but the use of parallel processing enables a vast improvement in speed. As the inputs to the final adder circuitry arrive in parallel, glitches are reduced, resulting in the lower power dissipation, the students reported.

They researchers claim the decomposition process can be extended further, to implement a 4 x 4 multiplier using two 2 x 4 multipliers or four 2 x 2 multipliers; but here the degradation caused by the extra circuitry outweighs the benefits derived from the parallel processing of data.

Simulation was done using TSpice for a design based on Taiwan Semiconductor Manufacturing Corp.'s (TSMC's) 180-nanometer technology.

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