Freescale 公司的MSC8113是高度集成的片上系统(SOC),它集成了三个StarCore® SC140内核,带硬件支持u/A律译码/编码的1024路时分复接(TDM),UART,16路DMA控制器,以太网控制器,1436KB SRAM以及灵活的系统接口单元(SIU),工作频率为300MHz 和400MHz,主要应用高宽带高度计算的DSP应用如无线代码转换,高密度分组电话DSP场(DSP farm),以及高带宽的基站.本文介绍了三核处理器MSC8113的主要性能,方框图以及内核SC140的方框图,以及Freescale所提供的开发工具和672 G.711通路媒体网关的应用案
The MSC8113 device is a highly integrated system-on-a-chip that combines three StarCore® SC140 cores,1024-channel time division multiplexing (TDM) with hardware support for /A-law decoding/encoding, a UART, a 16-channel DMA controller, an Ethernet controller, 1436 Kbyte of SRAM, and a flexible system interface unit (SIU). The MSC8113 device targets high-bandwidth, highly computational DSP applications and is optimized for high-bandwidth wireless transcoding and a high-density packet telephony DSP farm, as well as high-bandwidth base station applications. The MSC8113 delivers enhanced performance while maintaining low power dissipation and greatly reducing system cost. The MSC8113 is provided in two frequencies: 300 and 400 MHz.
Each SC140 core has four ALUs and performs at a rate of up to 1200/1600 DSP million multiply and accumulate commands per second (MMACS) with an internal 300/400 MHz clock at 1.1 V. The MSC8113 delivers a total performance of 3600/4800 DSP MMACS. Each SC140 core connects to a level-1 224 Kbyte internal memory (M1) for program and data storage as well as a 16 Kbyte, 16-way instruction cache and a 4-entry write buffer queue for boosting core performance. All the SC140 cores share an internal 476
Kbyte level 2 memory (M2).
The TDM interface can transfer up to 1024 channels in and out of the device. The Ethernet controller port can be used for board-level interconnect and connection between boards. A full-featured multi-master 60x-compatible system port enables the SC140 cores to access external devices and gives an external host direct access to the internal memories. A flexible memory controller supports glueless accesses to various
memory devices on the system bus, including SDRAM, DRAM, SRAM, Flash memory, EPROM, and user-definable memory. An external host can also access the MSC8113 device directly through a 32/64-bit direct slave interface (DSI) port. A flexible 16-channel DMA controller transfers data to and from the core M1, the M2 memory, and the serial interfaces.

MSC8113 Tri-Core Digital Signal Processor
The MSC8113 is a highly integrated system-on-a-chip that combines three StarCore SC140 extended cores with an RS-232 serial interface, four time-division multiplexed (TDM) serial interfaces, thirty-two general-purpose timers, a flexible system interface unit (SIU), an Ethernet interface, and a multi-channel DMA controller. The three extended cores can deliver a total 3600/4800 DSP MMACS performance at 300/400 MHz.
Each core has four arithmetic logic units (ALUs), internal memory, a write buffer, and two interrupt controllers. The MSC8113 targets high-bandwidth highly computational DSP applications and is optimized for wireless transcoding and packet telephony as well as high-bandwidth base station applications. The MSC8113 delivers enhanced performance while maintaining low power dissipation and greatly reduces system cost.
The MSC8113 device is designed to provide an optimal solution for 3G wireless base stations, to help eliminate many of the costly and power hungry ASICs and FPGAs required in todays systems for both symbol rate and for chip rate assist. In addition, the MSC8113 device allows customers to add next-generation features that efficiently use available frequencies and higher bit rates in 3G systems.
Efficient application software development is key in Freescales strategy to expedite customers time-to-market. Developers can take advantage of development tools and real-time operating systems (RTOS) from Metrowerks, a Freescale company, and third-party suppliers. In addition Freescale is partnering with third-party vendors to provide integrated systems solutions that include GSM, CDMA, TDMA, and ITU G.7xx speech coders, hybrid echo cancellation, fax, modem, and xDSL software.
Three StarCore SC140 DSP extended cores, each with an SC140 DSP core, 224 Kbyte of internal SRAM M1 memory (1436 Kbyte total), 16 way 16 Kbyte instruction cache (ICache), four-entry write buffer, external cache support, programmable interrupt controller (PIC), local interrupt controller (LIC), and low-power Wait and Stop processing modes.

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