Assuming that you build enough sourcing flexibility into your design to comprehend supply impermanence, PC-tailored microprocessors can provide a cost-effective means of achieving your system’s performance targets. And, with the PC industry’s amplified power-consumption focus, battery life, power-supply size, and heat dissipation aren’t the concerns they might have previously been, either. Traditional CPU and DSP suppliers haven’t stood still in the face of the PC-processor onslaught, however, and their alternative solutions remain optimal in many situations. A solid understanding of the historical trends, current status, and future plans of the primary x86 CPU suppliers will enable you to assess which path to take for your next design (see sidebar “Montalv-who?”).

Intel exemplifies how substantially a company’s fortunes can change in five short years. In the early portion of this decade, Intel based its entire microprocessor product line (laptops to servers), with the exception of the Itanium processor, on the NetBurst microarchitecture (see sidebar “Speeds and feeds”). NetBurst had lengthy pipelines—20 stages in the initial 180-nm Willamette variant, extending to as many as 31 stages in the final 90-nm Prescott and 65-nm Cedar Mill iterations. These pipelines performed well when code characteristics paired them with highly predictable multimedia-instruction streams. But the low IPC (instructions-per-clock) attribute inherent in any long-pipeline approach, combined with substantial branch-misprediction penalties, gave NetBurst underwhelming performance on more conventional code. And, in striving to boost clock rates as compensation for long-pipeline penalties, Intel ran into substantial leakage-current problems beginning at the 90-nm process node, which rendered the company’s NetBurst products 6.2 GHz short of the initial 10-GHz microarchitecture target. (Even getting to 3.8 GHz proved to be a formidable project.)

Intel’s fortunes began trending back upward, beginning in the mobile-computing segment, when, in the spring of 2003, it introduced the first Banias iteration of the Pentium M microarchitecture (Reference 1). Fabricated on a 130-nm process, Banias preceded the 90-nm-based Dothan with a larger L2 cache and 65-nm dual-core Yonah with a shared L2 cache (Reference 2). Pentium M leveraged and expanded on the execution unit of the Pentium III and coupled it to the Pentium 4 bus interface. As such, it offered more efficient power and instructions than NetBurst on a per-clock basis with conventional code traces. Yonah-generation CPUs, instead of using the Pentium M brand of their predecessors, employed a Core marketing moniker that proved somewhat confusing a short time later, when the company rolled out a suite of 65-nm-process-based Merom, Conroe, and Wolfdale CPUs, respectively spanning laptops to servers, and leveraging the follow-on Core microarchitecture, which the company marketed with the Core 2 promotion brand.

Intel is now shipping the second iteration of its Core microarchitecture, known as Penryn, which it fabricates on a 45-nm-process lithography. Penryn reflects the company’s “tick-tock” strategy, a product cadence that involves smaller lithography products, with only minor corresponding feature tweaks (tick), followed roughly one year later by a more substantive architecture revamp on a common process foundation (tock).

As such, the corresponding tock to today’s Penryn tick, Nehalem, ramps into production this year, and Intel is publicly demonstrating it in prototype-system form. Nehalem will address several longstanding AMD criticisms, albeit ones that few benchmarking tests to date have shown result in real-life performance shortcomings. Through today’s Penryn products, all intercore communication, with the exception of intradie shared-cache-coherency synchronization—whether within a die, between dice in a multidie monolithic-packaged CPU, or between packaged CPUs—occurs through the same front-side bus that carries data traffic to and from external subsystems. The primary external subsystem is the core-logic chip set, which in today’s designs contains the DRAM controller.

Nehalem-class CPUs integrate the dedicated QuickPath Interconnect interprocessor—formerly, CSI (common-system interface). The link is conceptually reminiscent of the HyperTransport link, which AMD introduced in 2001 for communications between multiple cores on a die and between multiple-die and packaged CPUs. Also reminiscent of technology AMD pioneered in 2003 with the Athlon 64 and Opteron K8 (also known as Hammer) CPUs, Nehalem-based products embed DRAM controllers to, among other things, reduce the extended latencies systems now experience when cache misses require external-memory accesses. And speaking of cache, whereas today’s Intel products go beyond two cores by combining multiple die under a common package lid, the prodigious transistor budget that the 45-nm process affords will enable the company to monolithically squeeze at least six CPU cores onto a single sliver of Nehalem-based Dunnington silicon (Figure 1). Each pair of cores, like other current products, shares a common L2 cache, and all six cores split a common L3 cache in the layout hole in which a fourth two-core cluster might otherwise go.

The 45-nm-process generation enables Intel to build not only cost-effective large-die products, but also very cost-effective small-die processors. That cost-effectiveness is the impetus for the Atom-CPU-product line, which Intel formally introduced at the Shanghai Intel Developer Forum in early April (Reference 3). Formerly Silverthorne, Atom combines with a single-chip companion device; Intel previously referred to the chip set as Menlow. Atom’s origins derive from the under-development and x86-based Larrabee PC coprocessor, intended for graphics, imaging, physics, and other functions. Intel’s architects determined that they required the ability to cost-effectively embed 16 or more x86 cores on a single Larrabee die and that the out-of-order execution and other exotic attributes of the company’s mainstream CPUs represented overkill for the targeted applications. Consequently, Intel went “back to the future,” dusting off its Pentium III schematics to come up with an area-optimized CPU-core design for Larrabee. The company is attempting to maximize its return on investment by also developing few-physical-core chips that it bases on the Larrabee atomic building block, some also with HyperThreading virtual-multicore support, for power- and cost-sensitive mobile systems.

First-generation Atom CPUs come in five versions, with clock speeds that reach 1.86 GHz and a TDP (thermal-design-power) range of 0.65 to 2.4W. Corresponding average- and idle-power ranges are, respectively, 160 to 220 mW and 80 to 100 mW. The partner system-controller hub, available in three versions, features a 3-D graphics core; a hardware-accelerated, high-definition-video-decoding engine; high-definition-audio processing; and support for PCI (peripheral-component-interconnect) Express, USB, and SDIO (secure-digital-input/output) connectivity. And, with long-life-cycle embedded-system designs in mind, Intel promises at least seven years of product support. A planned dual-core Atom variant will be more compelling in low-cost laptop and desktop systems, and Intel also plans an even more integrated single-chip, albeit perhaps multidie, Moorestown Atom family for next year. All in all, after years of stumbling, Intel’s seemingly back in full stride. Perhaps the biggest question on the company’s road map for the remainder of the decade is the degree to which Atom will cannibalize Intel products in a manner that is fiscally unattractive to Intel, instead of broadening the overall x86 market at the expense of competitors, such as ARM, as Intel hopes.

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