The AVR32 UC3 integrates SRAM in the three-stage pipeline, dual-bank architecture. This bypasses the system bus to achieve faster execution, cycle determinism, and lower power consumption. A HSB (high-speed bus) slave interface allows DMA controllers or other HSB masters to write to or read data directly from the closely coupled SRAM. Arbitration is performed if the CPU and a high-speed slave request access simultaneously, and the priority scheme is programmable to suit specific applications needs. The UC3 core pipeline presents no data hazards, so the processor can update the register files during the same clock cycle as it executes the instruction.

The AVR32 UC3 is the second core derived from the AVR32 AP architecture; it is a 32-bit RISC core with instruction extensions that add DSP instructions to the instruction set of the original core. The DSP instructions include single-cycle MAC (multiply-accumulate) operations covering standard and fractional numbers, both with and without saturation and rounding, and with 32- to 64-bit results. Additional DSP instructions include data-formatting instructions such as data shift with saturation and rounding.

The ISA (Instruction Set Architecture) permits freely intermixing 16- and 32-bit instructions. The AVR32 UC3 core shares the ISA with its AVR32 AP parent, with over 220 instructions available as 16-bit compact and 32-bit extended instructions. Load/store instructions support byte (8-bit), half-word (16-bit), word (32-bit), and double-word (64-bit) data types. The AVR32 ISA has instructions to modify data read from the register file before storing it to memory, and read from memory before storing it to the register file. On-the-fly data manipulations include load-and-insert bit fields, load-and-swap, and store-and-swap. The UC3 ISA includes atomic instructions to manipulate mutexes and semaphores, and for general bit-manipulation.

The AVR32 UC3 core includes power-management functions, a memory-protection unit, and a six-level priority interrupt controller including NMI (nonmaskable interrupt) with fast event handling. The core's event-handling system support events like NMI, exceptions (illegal opcode, bus error), and four interrupt-priority levels. The first instruction from the event handler is executed within 12 clock cycles, from an autovectored handler address. To limit the maximum interrupt latency to 16 clock cycles, pending interrupts can abort multicycle instructions.

The UC3 Series A microcontrollers include a peripheral DMA controller, a multilayer, high-speed bus architecture, a 10/100 Ethernet MAC (media access controller), an ADC (analog to digital converter), two master/slave SPIs (serial peripheral interfaces), one SSC (synchronous serial communication) interface, a TWI (two-wire interface), four USARTs with hardware flow-control, and full-speed USB OTG. The microcontrollers are available with an external bus interface that extends the addressable physical memory to 16 Mbytes. The nonmultiplexed 16-bit data bus can interface to high-density external SRAM, SDRAM, ROM, flash devices, and memory-mapped devices such as LCDs or FPGAs. The devices include three 16-bit timers and seven PWMs (pulse width modulators) that can trigger the 10-bit, 8-channel ADC to ease electrical-motor-control design.

The on-chip system manager includes an internal voltage regulator for 3.3V single-power-supply operation, power-on reset, brown-out detector, hardware watchdog timer, and a real-time timer. The clock system provides an on-chip RC oscillator, two high-frequency external oscillators, one 32-kHz oscillator, and two independent on-chip PLLs. Special security options are available to protect the flash contents. The device consumes 40 µA in sleep mode and 600 µA/MHz in active mode. Any section of the UC3A device that is not in use can be switched off by disabling its clock. The UC3 core uses a multithreshold transistor library to reduce static power consumption.

Atmel provides the GNU gcc C compiler, GNU gdb debugger, FreeRTOS.org real-time kernel, and lwIP TCP/IP protocol stack for the UC3 Series A family, free of charge. Atmel's AVR32 Studio and AVR JTAGICE mkII, used with Atmel's 8-bit AVR microcontrollers, provide the AVR32 UC3 with a multiplatform integrated development environment already configured for the GNU tool chain, including support for more advanced debugging sessions with data and code trace using the AVR32's Nano Trace. The AVR32 UC3 has a Nexus class 2+ interface through the auxiliary (AUX) port that gives access to more powerful debugging features including nonintrusive data and program trace. An available evaluation kit (EVK1100) includes Ethernet and USB interfaces, as well as SPI, TWI, and USARTS. A 20×4-character LCD and the expansion connector allow advanced evaluation and prototyping.

The first two devices of the UC3 Series A are sampling now and will be available in volume production in Q4. The AT32UC3A0512, with an EBI (external bus interface) and 512 kbytes of flash, is available in a QFP144 for $8.16 (10,000). The AT32UC3A1512, without an EBI and 512 kbytes of flash, is available in a QFP100 package for $7.43 (10,000).