| Lattice LatticeMico32开发方案 |
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| 作者：未知 来源：Lattice 点击数：139 更新时间：2008-7-11 |
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Lattice 公司的LatticeMico32是32位哈佛RISC架构的软微处理器,可提供公开IP核许可证协议. LatticeMico32把32位宽指令集和32位通用寄存器组合在一起,能处理多达32个外部中断,有多种外设,为各种市场的应用提供优异的性能和灵活性.本文介绍了LatticeMico32的主要特性和优势,方框图, 系统开发流程以及LatticeMico32/DSP开发板的主要特性, 方框图,各种接口以及开发板的详细电路图.
The LatticeMico32™ is a highly configurable 32-bit Harvard architecture “soft” microprocessor core for Lattice Field Programmable Gate Array (FPGA) devices. By combining a 32-bit wide instruction set with 32 general purpose registers, the LatticeMico32 provides the performance and flexibility suitable for a wide variety of markets. Using a Reduced Instruction Set Computer (RISC) architecture, the core consumes minimal device resources, while maintaining the performance required for a broad application set. The associated LatticeMico32 System Development Tools provide a fast and easy way to implement microprocessor designs. The tools enable processor platform definition, software develop¬ment and debug. Additionally, the LatticeMico32 is available as source code under the Lattice open IP core license, thereby providing visibility, flexibility and portability – all free of charge.
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