Silicon Lab 公司的Si4702/03C FM收音机调谐器集成了从天线输入到立体声音频输出的全部功能. Si4703-C采用适合于欧洲无线电系统(RDS)和US无线电广播数据系统(RBDS)的数字处理器,包括符号译码所需的所有功能,同步区块,误差检测以及误差修正等,支持世界范围的FM广播频率76–108 MHz. Si4702/03C广泛应用于手机,MP3播放器,手提收音机,USB FM收音机,PDA,笔记本电脑,消费类电子以及手提导航系统.本文介绍了Si4702/03C的详细特性,方框图以及典型应用电路和材料清单(BOM).

BROADCAST FM RADIO TUNER FOR PORTABLE
The Si4702/03 integrates the complete tuner function from antenna input to stereo audio output for FM broadcast radio reception.
The Si4702/03-C19 extends Silicon Laboratories Si4700/01 FM tuner family, and further increases the ease and attractiveness of adding FM radio reception to mobile devices through small size and board area, minimum component count, flexible programmability, and superior, proven performance. Si4702/03-C19 software is backwards compatible to existing Si4700/01 and Si4702/03-B16 FM Tuner designs. The Si4702/03-C19 benefits from proven digital integration and 100% CMOS process technology, resulting in a completely integrated solution. It is the industrys
smallest footprint FM tuner IC requiring only 10 mm2 board space and one external bypass capacitor.

The device offers significant programmability, and caters to the subjective nature of FM listeners and variable FM broadcast environments world-wide through a simplified programming interface and mature functionality.

The Si4703-C incorporates a digital processor for the European Radio Data System (RDS) and the US Radio Broadcast Data System (RBDS) including all required symbol decoding, block synchronization, error detection, and error correction functions. RDS enables data such as station identification and song name to be displayed to the user. The Si4703-C offers a detailed RDS view and a standard view, allowing adopters to selectively choose granularity of RDS status, data, and block errors. Si4703-C software is backwards compatible to the proven Si4701, adopted by leading cell-phone and MP3 manufacturers world-wide.

The Si4702/03-C19 is based on the superior, proven performance of Silicon Laboratories Aero architecture offering unmatched interference rejection and leading sensitivity. The device uses the same programming interface as the Si4701 and supports multiple bus-modes. Power management is also simplified with an integrated regulator allowing direct connection to a 2.7 to 5.5 V battery.
The Si4702/03-C19 device’s high level of integration and complete FM system production testing increases quality to manufacturers, improves device yields, and simplifies device manufacturing and final testing.

FM Receiver
The Si4702/03-C19’s patented digital low-IF architecture reduces external components and
eliminates the need for factory adjustments. The receive (RX) section integrates a low noise amplifier (LNA) supporting the worldwide FM broadcast band (76 to 108 MHz). An automatic gain control (AGC) circuit controls the gain of the LNA to optimize sensitivity and rejection of strong interferers. For testing purposes, the AGC can be disabled with the AGCD bit. Refer to Section 6. Register Descriptions on page 23 for additional programming and configuration information.

The Si4702/03-C19 architecture and antenna design increases system performance. To ensure proper performance and operation, designers should refer to the guidelines in AN231: Si4700/01/02/03 Headphone and Antenna Interface. Conformance to these guidelines will help to ensure excellent performance even in weak signal or noisy environments.

An image-reject mixer downconverts the RF signal to low-IF. The quadrature mixer output is amplified, filtered, and digitized with high resolution analog-to-digital converters (ADCs). This advanced architecture achieves superior performance by using digital signal processing (DSP) to perform channel selection, FM demodulation, and stereo audio processing compared to traditional analog architectures.
General Purpose I/O Pins
The pins GPIO1–3 can serve multiple functions. GPIO1 and GPIO3 can be used to select between 2-wire and 3-wire modes for the control interface as the device is brought out of reset. See Section “4.9. Reset, Powerup, and Powerdown”. After powerup of the device, the GPIO1–3 pins can be used as general purpose inputs/outputs, and the GPIO2–3 pins can be used as interrupt request pins for the seek/tune or RDS ready functions and as a stereo/mono indicator respectively.
It is recommended that the GPIO2–3 pins not be used as interrupt request outputs until the powerup time has completed (see Section “4.9. Reset, Powerup, and Powerdown”). The GPIO3 pin has an internal, 1 MΩ, ±15% pull-down resistor that is only active while RST is low. General purpose input/output functionality is available regardless of the state of the VA and VD supplies, or the ENABLE and DISABLE bits.

RDS/RBDS Processor and Functionality
The Si4703 implements an RDS/RBDS* processor for symbol decoding, block synchronization, error detection, and error correction. RDS functionality is enabled by setting the RDS bit. The device offers two RDS modes, a standard mode and a verbose mode.

The primary difference is increased visibility to RDS block-error levels and synchronization status with verbose mode.

Setting the RDS mode (RDSM) bit low places the device in standard RDS mode (default). The device will set the RDS ready (RDSR) bit for a minimum of 40 ms when a valid RDS group has been received. Setting the RDS interrupt enable (RDSIEN) bit and GPIO2[1:0] = 01 will configure GPIO2 to pulse low for a minimum of 5 ms when a valid RDS group has been received. If an nvalid
group is received, RDSR will not be set and GPIO2 will not pulse low. In standard mode RDS synchronization (RDSS) and block error rate A, B, C and D (BLERA, BLERB, BLERC, and BLERD) are unused and will read 0. This mode is backward compatible with earlier firmware revisions.
Setting the RDS mode bit high places the device in RDS verbose mode. The device sets RDSS high when synchronized and low when synchronization is lost. If the device is synchronized, RDS ready (RDSR) will be set for a minimum of 40 ms when a RDS group has been received. Setting the RDS interrupt enable (RDSIEN) bit and GPIO2[1:0] = 01 will configure GPIO2 to pulse low for a minimum of 5 ms if the device is synchronized and an RDS group has been received.
BLERA, BLERB, BLERC and BLERD provide block-error levels for the RDS group. The number of bit errors in each block within the group is encoded as follows: 00 = no errors, 01 = one to two errors, 10 = three to five errors, 11 = six or more errors. Six or more errors in a block indicate the block is uncorrectable and should not be used.

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