ADI公司的ADSP-BF538/ADSP-BF538F处理器是Blackfin处理器,采用ADI和Intel的MSA架构,有双MAC的信号处理引擎,正交RISC类的微处理器指令集,以及单指令多数据(SIMD)多媒体功能. ADSP-BF538工作频率高达533MHz,有两个16位MAC,两个40位ALU,四个8位视频ALU以及40位移位寄存器.内核工作电压0.85V到1.25V,I/O电压为2.5V到3.3V. ADSP-BF538还有丰富的外设和接口,可广泛应用在工业控制,仪器仪表,医疗设备和安全系统.本文介绍了ADSP-BF538/ADSP-BF538F处理器的主要性能,方框图以及ADSP-BF538F EZ-KIT LITE评估板及其详细电路图.

Blackfin Embedded Processor ADSP-BF538/ADSP-BF538F
The ADSP-BF538/ADSP-BF538F processors are members of the Blackfin® family of products, incorporating the Analog Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction set architecture.

The ADSP-BF538/ADSP-BF538F processors are completely code compatible with other Blackfin processors, differing only with respect to performance, peripherals, and on-chip memory.

ADSP-BF538主要特性:
Up to 533MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter RISC-like register and instruction model for ease of programming and compiler friendly support
Advanced debug, trace, and performance monitoring
0.85 V to 1.25 V core VDD with on-chip voltage regulation
2.5 V to 3.3 V I/O VDD
Up to 3.3 V tolerant I/O with specific 5 V tolerant pins
316-ball Pb-free CSP_BGA package
MEMORY
148K bytes of on-chip memory:
16K bytes of instruction SRAM/cache
64K bytes of instruction SRAM
32K bytes of data SRAM
32K bytes of data SRAM/cache
4K bytes of scratchpad SRAM
512K _ 16-bit or 256K _ 16-bit flash memory (ADSP-BF538F only)
Memory management unit providing memory protection
External memory controller with glueless support for SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI and external memory
PERIPHERALS
Parallel peripheral interface (PPI) supporting ITU-R 656 video data formats
4 dual-channel, full-duplex synchronous serial ports, supporting 16 stereo I2S channels
2 DMA controllers supporting 26 peripheral DMAs
4 memory-to-memory DMAs
Controller area network (CAN) 2.0B controller
3 SPI-compatible ports
Three 32-bit timer/counters with PWM support
3 UARTs with support for IrDA
2 TWI controllers compatible with I2C industry standard
Up to 54 general-purpose I/O pins (GPIO)
Real-time clock, watchdog timer, and 32-bit core timer
On-chip PLL capable of 0.5_ to 64_ frequency multiplication
Debug/JTAG interface



图1. ADSP-BF538方框图



图2.Blackfin处理器内核方框图
ADSP-BF538评估板ADSP-BF538F EZ-KIT Lite
The evaluation board is designed to be used in conjunction with the VisualDSP++
® development environment to test the capabilities of the ADSP-BF538F Blackfin processors. The VisualDSP++ development environment gives you the ability to perform advanced application code development and debug, such as:
Create, compile, assemble, and link application programs written in C++, C, and ADSP-BF538F assembly
Load, run, step, halt, and set breakpoints in application programs
Read and write data and program memory
Read and write core and peripheral registers
Plot memory
ADSP-BF538F EZ-KIT Lite 评估板主要特性:
Analog Devices ADSP-BF538F processor
Core performance up to 600 MHz
External bus performance to 133 MHz
182-pin mini-BGA package
25 MHz crystal
Synchronous dynamic random access memory (SDRAM)
MT48LC32M8 – 64 MB (8M x 8-bits x 4 banks) x 2 chips
Flash memory
4MB (2M x 16-bits)
Analog audio interface

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