| ST ST7540动力线调制解调方案 |
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| 作者：未知 来源：ST 点击数：392 更新时间：2008-7-31 |
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ST公司的ST7540是 FSK动力线收发器，半双工异步／同步FSK调制解调器. ST7540集成了线路驱动器和5V 和3.3V线性稳压器，单电源7.5 到13.5 V工作．器件通过内部的寄存器来控制工作，可通过同步串行接口进行可编程．其它的功能包括看门狗，时钟输出，输出电流和电压控制，载波／前导检测，发送停止和信道在用与热关断等．ST7540可以采用八个不通的信道(60, 66, 72,76, 82.05, 86, 110, 132.5 kHz)进行通信，有四种不同的波特率(600, 1200, 2400, 4800)和两种精度（1 和0.5）．本文介绍了ST7540的主要性能，方框图
,参考设计的主要特性和评估板电路图以及所用的材料清单（BOM）.
ST ST7540 FSK powerline transceiver
ST7540 transceiver uses Frequency Shift Keying (FSK) modulation to perform a half-duplex communication on a powerline network. It operates from a 7.5 to 13.5 V single supply voltage (Vcc) and integrates a power amplifier (PA), which is able to drive low line impedance, and two linear regulators providing 5 V and 3.3 V.
The ST7540 can communicate using eight different communication channels (60, 66, 72,
76, 82.05, 86, 110, 132.5 kHz), four baud rates (600, 1200, 2400, 4800) and two deviations (1 and 0.5). Additional functions are included, such as watchdog, automatic control on PA output voltage and current, carrier/preamble detection and band-in-use signaling, transmission time-out, and thermal shutdown.
The transceiver, which is dedicated only to physical communication, operates with a
microcontroller whose aim is to manage the communication protocol stack. A reset output
(RSTO) and a programmable clock (MCLK) can be provided to the microcontroller by the
ST7540 in order to simplify the external logic and circuitry.
The host controller can exchange data with the transceiver through a serial interface,
programmable to operate either in UART (CLR/T data clock not used) or in SPI mode.
Communication on the power line can be either synchronous or asynchronous to the data
clock that is provided by the transceiver at the programmed baud rate.
When in transmission mode (i.e. RxTx line at low level), the ST7540 samples the digital
signal on the TxD line at the programmed baud rate and modulates it in a FSK sinusoidal
output on the Tx_OUT line. This signal is then externally fed into the power amplifier to add current capability. The power amplifier can also introduce gain and active filtering to the signal, just using few external passive components. The resulting signal on the PA_OUT line is coupled to the power line.
When in receiving mode (i.e. RxTx line at high level), an incoming FSK signal on the Rx_IN line is demodulated and the digital output is available for the microcontroller on the RxD pin.
The device also recovers the synchronism of the received signal using an internal PLL. The recovered clock is present on CLR/T output.
The ST7540 operating parameters can be set by means of an internal control register,
accessible only through the SPI host interface.
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