When synchronizing two instruments’ signals, it is important to make sure that the receiver can latch the sender’s synchronous signal. For example, a pulse generator generates synchronizing pulses while generating the main pulse signal. For the Avtek AV-1015B, the pulse generator’s duty cycle is approximately 50 nsec at TTL with a 50Ω load. The goal of this Design Idea is to increase the pulse generator’s high-level width to meet the triggering spec of a lock-in amplifier. The synchronizing pulse’s frequency is 10 Hz to 102 kHz, which is the lock-in amplifier’s frequency range.

Because the synchronizing pulse synchronizes to the main pulse, you must minimize any delay in calculating the lock-in amplifier’s synchronizing input. And, because the user can change the frequency of the pulse train from the pulse generator, the synchronizing signal’s frequency also changes. Therefore, you must make sure that the circuit properly calculates and generates the synchronizing signal, no matter how the user sets the output of the pulse generator.

Figure 1 shows the half-duty-cycle generator’s algorithm. The CPLD first waits for the positive-edge trigger, then starts to count at a frequency of 60 MHz, and waits for the next positive-edge trigger. When the next positive edge comes, the synchronizing signal’s period counting is complete. The counting value then gets saved in a buffer and divided by 2 to yield the value for half-duty-cycle generation.

In tests, the half-duty-cycle generator in this Design Idea worked over a frequency range of 2 Hz to 450 kHz. You can use this design not only in a pulse generator, but also in any synchronizing signal in which the pulse is too narrow for other system triggering. The half-duty-cycle generator fits into a CPLD, such as an Altera EPM570 with a 60-MHz system clock and an MM74HCT244 buffer to output a TTL signal. Listing 1 contains the program for the CPLD.

assign oSynPulse  =  (mCount<=mCount2)? 1:0 ; //Output the 50% duty          cycle pulse

endmodule