TI公司的TMS320DM355 DaVinci数字媒体处理器是高度集成可编程的平台,适用于数码相机,数码相框,IP安全照相机,4路数字视频记录仪,视频门铃以及其它低成本的手提数字视频应用.本文介绍了采用DM355的视频IP网络照相(IPNC)参考设计的硬件特性,软件特性,DM355的主要特性以及图像传感器MT9P031的特性和方框图.此外,还介绍了IPNC的系统方框图. Texas Instruments offers three different highly optimized reference designs based on the TMS320DM355 DaVinci&#8482; digital media processor for the IPNC market to enable developers to speed through the design process as well as reducing overall bill of materials costs. These solutions reduce development to under four months by including: Complete and optimized schematics Gerber fi les Free Linux application source code, including: Integrated auto white balance and auto exposure Simple motion detection Dual-stream HD MPEG-4 and MJPEG video codecs to support recording and monitoring needs at full frame rates DaVinci IP Netcam software framework including I/O application programming interfaces (APIs), media APIs and DaVinci Codec Engine 参考设计硬件特性: TMS320DM355 SoC, ARM926 and hardware video coprocessor Aptina 5 MP sensor (2 x 2 binning ~1.3 MP) CMOS imager optimized for low-light performance Board size 65 x 50 mm Low-power (< 3 W) 参考设计软件特性: Complete Linux-based IP network camera application including free source code Dual-stream capabilities Integrated auto white balance and auto exposure Field-proven, robust, royalty-free bundled MPEG-4 and MJPEG video codecs DaVinci IPNC software framework including I/O APIs, media APIs and DaVinci Codec Engine Ability to add video analytics with DaVinci TMS320DM643x digital media processors 图1.基于TMS320DM355参考设计软件框图 TMS320DM355 DaVinci处理器 The DM355 is a highly integrated, programmable platform for digital still camera, digital photo frames, IP security cameras, 4-channel digital video recorders, video door bell application, and other low cost portable digital video applications. Designed to offer portable video designers and manufacturers the ability to produce affordable portable digital video solutions with high picture quality, the DM355 combines high performance MPEG4 HD (720p) codecs and JPEG codecs up to 50M pixels per second, high quality, and low power consumption at a very low price point. The DM355 also enables seamless interface to most additional external devices required for a complete digital camera implementation. The interface is flexible enough to support various types of CCD and CMOS sensors, signal conditioning circuits, power management, DDR/mDDR memory, SRAM, NAND, shutter, Iris and auto-focus motor controls, etc. The DM355 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. 主要特性: High-Performance Digital Media System-on-Chip 135-, 216- and 270-MHz ARM926EJ-S Clock Rate Fully Software-Compatible With ARM9 Extended Temperature 216-Mhz Devices are Available ARM926EJ-S Core Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets DSP Instruction Extensions and Single Cycle MAC ARM&reg; Jazelle&reg; Technology EmbeddedICE-RT&#8482; Logic for Real-Time Debug ARM9 Memory Architecture 16K-Byte Instruction Cache 8K-Byte Data Cache 32K-Byte RAM 8K-Byte ROM Little Endian MPEG4/JPEG Coprocessor Fixed Function Coprocessor Supports: MPEG4 SP Codec at HD (720p), D1, VGA, SIF JPEG Codec up to 50M Pixels per Second Video Processing Subsystem Front End Provides: Hardware IPIPE for Real-Time Processing up to 14-bit CCD/CMOS Digital Interface 16-/8-bit Generic YcBcR-4:2 Interface (BT.601) 10-/8-bit CCIR6565/BT655 Interface Up to 75-MHz Pixel Clock Histogram Module Resize Engine Resize Images From 1/16x to 8x Separate Horizontal/Vertical Control Two Simultaneous Output Paths Back End Provides: Hardware On-Screen Display (OSD) Composite NTSC/PAL video encoder output 8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface Supports digital HDTV (720p/1080i) output for connection to external encoder External Memory Interfaces (EMIFs) DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O) Asynchronous16-/8-bit Wide EMIF (AEMIF) Flash Memory Interfaces NAND (8-/16-bit Wide Data) OneNAND(16-bit Wide Data) Flash Card Interfaces Two Multimedia Card (MMC) / Secure Digital (SD/SDIO) SmartMedia Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) USB Port with Integrated 2.0 High-Speed PHY that Supports USB 2.0 Full and High-Speed Device USB 2.0 Low, Full, and High-Speed Host Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers) One 64-Bit Watch Dog Timer Three UARTs (One fast UART with RTS and CTS Flow Control) Three Serial Port Interfaces (SPI) each with two Chip-Selects One Master/Slave Inter-Integrated Circuit (I2C) Bus&reg; Two Audio Serial Port (ASP) I2S and TDM I2S AC97 Audio Codec Interface S/PDIF via Software Standard Voice Codec Interface (AIC12) SPI Protocol (Master Mode Only) Four Pulse Width Modulator (PWM) Outputs Four RTO (Real Time Out) Outputs Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions) On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART Configurable Power-Saving Modes Crystal or External Clock Input (typically 24 MHz or 36 MHz) Flexible PLL Clock Generators Debug Interface Support IEEE-1149.1 (JTAG) Boundary-Scan-Compatible ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory Device Revision ID Readable by ARM 337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch 90nm Process Technology

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